In this work, a smart reconfigurable Multi-Processor Systems-on-Chip (ASREM) has been introduced. The researcher examined a reconfigurable MPSoC architecture that incorporates one Processor-FPGA core to ensure flexibility and better design parameters. The objective of this work is to initiate a smart system that introduces this philosophy: the system would build a better system by itself. The system would learn about usage statistics by using an android application with the help of support vector machine (SVM) algorithm. Accomplishing this, the system would form a decision function from the SVM classifier to improve usability. According to the user’s preference, it would re-design the reconfigurable MPSoC to ensure customized and superior user experience. A Reconfigurable MPSoC architecture and task scheduling mechanism has been introduced to enable the design. An image processing task has been performed as a case-study on a FPGA-SoC platform and GPU as a proof of concept to ensure current standards. The novel and competent approach of designing system for hand-held devices adopted in this study enables customization of the device after manufacturing.
|Commitee:||Kumar, Ashok, Zhao, Danella|
|School:||University of Louisiana at Lafayette|
|School Location:||United States -- Louisiana|
|Source:||DAI-B 78/04(E), Dissertation Abstracts International|
|Keywords:||Android application, Association rule mining, Multi-processor systems-on-chip, Reconfigurable computing, Support vector machine|
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