Dissertation/Thesis Abstract

Design of a low power asynchronous Viterbi decoder for wireless communications
by Deshpande, Parikshit, M.S., California State University, Long Beach, 2016, 47; 10142986
Abstract (Summary)

Rapid developments in the communications field have created a rising demand for low power, high speed, and low weight communication devices. The current project presents the development of a Viterbi decoder on a chip with a reduced dynamic power consumption, achieved by using an asynchronous design, which is data driven and active only when needed. The Xpower analyzer tool is used to measure the dynamic power on the designed chip, from which it is seen that the proposed design greatly improves power consumption. The results also show that there is a trade-off between dynamic power reduction, larger chip area, and reduced speed.

Indexing (document details)
Advisor: Chassiakos, Anastasios
Commitee: Ary, James, Khoo, I-Hung
School: California State University, Long Beach
Department: Electrical Engineering
School Location: United States -- California
Source: MAI 55/06M(E), Masters Abstracts International
Subjects: Electrical engineering
Keywords: Asynchronous, Low power, Viterbi decoder
Publication Number: 10142986
ISBN: 978-1-339-98240-3
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