This project report presents a Field Programmable Gate Array (FPGA) implementation of an adaptive receiver designed and patented by Dr. Rajendra Kumar, U.S. patent 8233568, July 31, 2012. This adaptive receiver is generally used in the systems where higher order modulated signals are used for transmitting information over a fading a channel.
In communication systems, a receiver design must be reliable. Previously, the adaptive receivers made use of pilot signals in order to correct the phase of the transmitted signal. However, this system faced challenges and failed to accurately detect the higher order modulated signals. To eliminate this challenge, the adaptive receiver designed and patented by Dr. Rajendra Kumar estimates the channel fade and the phase using an estimator, phase detector, and Kalman filter that decodes the data and provides the required channel equalization without the need of any pilot symbols.
This project efficiently implements Rajendra Kumar’s Adaptive Receiver on FPGA with reduced number of gates. Very High Speed Integrated Circuit Hardware Description Language (VHDL) codes and Xilinx ISE are used for replicating the adaptive receiver’s circuit on Nexys 3 Spartan-6 FPGA trainer board.
|Commitee:||Ary, James, Chassiakos, Anastasios|
|School:||California State University, Long Beach|
|School Location:||United States -- California|
|Source:||MAI 55/06M(E), Masters Abstracts International|
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