Power consumption and required area are two important features of an integrated circuit design. A computationally demanding circuit consists of millions of flip-flops working in a sequential process that is driven by a high frequency clock. In this project, the goal is to reduce power consumption, along with the area of a given logic circuit, by using a Multi-Bit Flip-Flop (MBFF) methodology, replacing Single-Bit Flip-Flops (SBBF). The MBFF uses a shared single clock input and has the same functionality of two SBFFs. A regular shift register is designed using MBFFs, and all the possible combinations have been analyzed for merging and replacement techniques. The designs have been implemented in Xilinx and the layout in Microwind software. Simulation results show that the area utilization and the power consumption of a 16-bit shift register using MBFF have been reduced by 41% and 21%, respectively, as compared to the equivalent SBFF design.
|Commitee:||Ary, James, Chassiakos, Anastasios, Tran, Boi|
|School:||California State University, Long Beach|
|School Location:||United States -- California|
|Source:||MAI 55/06M(E), Masters Abstracts International|
|Keywords:||Computationally demanding circuit, Flip-flop, Multi-bit, Power consumption|
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