Dissertation/Thesis Abstract

An efficient architecture for adaptive finite impulse response filters on field programmable gate arrays
by Nallani Chakravartula, Krishna Chaitanya, M.S., California State University, Long Beach, 2016, 56; 10137445
Abstract (Summary)

Digital filters are software programmable and play a crucial role in the operation of everyday electronic devices. The current project presents the architecture of a digital filter, specifically an adaptive Finite Impulse Response (FIR) filter, using a Field Programmable Gate Array (FPGA) instead of a Digital Signal Processor (DSP). The FIR filter's performance is evaluated by its throughput, power consumption, and the physical footprint of the implementation (required area). High throughput and a small footprint can be achieved by reducing the delay and utilizing look up tables, slices, and flip-flops. The current project presents a new architecture for an adaptive FIR filter based on Distributed Arithmetic(DA). Simulation results for filter lengths N=4 and N=16 show that the proposed FPGA-based architecture achieves higher throughput, lower power consumption, and requires a smaller area, as compared to DSP-based implementations.

Indexing (document details)
Advisor: Chassiakos, Anastasios
Commitee: Ary, James, Khoo, I-Hung
School: California State University, Long Beach
Department: Electrical Engineering
School Location: United States -- California
Source: MAI 55/06M(E), Masters Abstracts International
Subjects: Engineering, Electrical engineering
Publication Number: 10137445
ISBN: 978-1-339-93138-8
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