Dissertation/Thesis Abstract

Productive Design of Extensible On-Chip Memory Hierarchies
by Cook, Henry Michael, Ph.D., University of California, Berkeley, 2016, 153; 10150942
Abstract (Summary)

As Moore’s Law slows and process scaling yields only small returns, computer architecture and design are poised to undergo a renaissance. This thesis brings the productivity of modern software tools to bear on the design of future energy-efficient hardware architectures.

In particular, it targets one of the most difficult design tasks in the hardware domain: Coherent hierarchies of on-chip caches. I have extended the capabilities of Chisel, a new hardware description language, by providing libraries for hardware developers to use to describe the configuration and behavior of such memory hierarchies, with a focus on the cache coherence protocols that work behind the scenes to preserve their abstraction of global shared memory. I discuss how the methods I provide enable productive and extensible memory hierarchy design by separating the concerns of different hierarchy components, and I explain how this forms the basis for a generative approach to agile hardware design.

This thesis describes a general framework for context-dependent parameterization of any hardware generator, defines a specific set of Chisel libraries for generating extensible cache-coherent memory hierarchies, and provides a methodology for decomposing high-level descriptions of cache coherence protocols into controller-localized, object-oriented transactions.

This methodology has been used to generate the memory hierarchies of a lineage of RISC-V chips fabricated as part of the ASPIRE Lab’s investigations into application-specific processor design.

Indexing (document details)
Advisor: Patterson, David
Commitee: Asanovic, Krste, Wright, Paul
School: University of California, Berkeley
Department: Electrical Engineering and Computer Sciences
School Location: United States -- California
Source: DAI-B 77/12(E), Dissertation Abstracts International
Subjects: Computer Engineering, Computer science
Keywords: Agile development, Cache coherence, Hardware design, Memory hierarchy, Risc-v, Tilelink
Publication Number: 10150942
ISBN: 978-1-369-05706-5
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