The complexity of the manufacturing process has motivated manufacturers to consider testability as a requirement to assure the reliability and the functionality of each of their designed circuits. One of the most well-known test techniques is called Built-In-Self-Test (BIST). A BIST Universal Asynchronous Receive/Transmit (UART) has the objectives to firstly satisfy specified testability requirements and to secondly generate the lowest-cost with the highest performance implementation. UART has been an important input/output tool for decades and is still widely used. Although BIST techniques are becoming more common in industry, the additional BIST circuit that increases the hardware overhead increases design time and performance degradation is often cited as the reason for the limited use of BIST.
This project focuses on the design of a UART chip with embedded BIST architecture using Field Programmable Gate Array (FPGA) technology. The paper describes the problems of Very-Large-Scale-Integrated (VLSI) testing followed by the behavior of UART circuit using Verilog. In the implementation phase, the BIST technique will be incorporated into the UART design before the overall design is synthesized by means of reconfiguring the existing design to match testability requirements. The UART is targeted at broadband modems, base stations, cell phones and other designs. BIST is a design technique that allows a circuit to test itself. In this project, the test performance achieved with the implementation of BIST is proven to be adequate to offset the disincentive of the hardware overhead produced by the additional BIST circuit. The technique can provide shorter test time compared to an externally applied test and allows the use of low-cost test equipment during all stages of production.
|Commitee:||Ary, James, Chassiakos, Anastasios|
|School:||California State University, Long Beach|
|School Location:||United States -- California|
|Source:||MAI 55/05M(E), Masters Abstracts International|
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