In this thesis a 10-bit pipeline architecture of analog-to-digital converter (ADC) which is implemented in 65nm CMOS technology is presented. The nominal supply voltage is 1.0, and the power consumption of the 10-bit ADC is 1.5 mW when an input signal with 10 MHz clock frequency is applied. In this thesis, we introduced the pipeline ADC architecture which consists of sample and hold circuit, multiplying digital-to analog converter(MDAC) circuit, sub-ADC, digital delay correction circuit. Base on the theory and analysis, we purposed a 10-bit pipeline ADC structure and simulated it by using Cadence and Spectre simulation tools. Simulation result and non-idealities analysis show the 10-bit ADC is successfully working.
|Commitee:||Khodayar, Mohammad, You, Jeong Ho|
|School:||Southern Methodist University|
|School Location:||United States -- Texas|
|Source:||MAI 55/04M(E), Masters Abstracts International|
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