Dissertation/Thesis Abstract

64-bit area efficient binary adder in quantum-dot cellular automata
by Gudala, Niharika, M.S., California State University, Long Beach, 2016, 60; 10108192
Abstract (Summary)

With the decrease in transistor size, more and more transistors can be fabricated onto a single chip, consequently increasing the computational capabilities of the chip. As we reduce the transistor size we face challenges like high circuit resistance, quantized charge and more heat generation due to large circuit capacitance. Quantum-dot Cellular Automata (QCA) is one of a solution to overcome the physical limit of the transistor. The basic concept of QCA is the physical implementation of Cellular Automata (CA) in quantum-dots. This project demonstrates a new binary adder circuit, which will surpass all previous models and achieves better area-delay performance under binary additions. The designed 64-bit adder is shown to achieve a worst case delay of 15ns with overall reduced area of 18.72μm2.

Indexing (document details)
Advisor: Chassiakos, Anastasios
Commitee: Ary, James, Tran, Boi
School: California State University, Long Beach
Department: Electrical Engineering
School Location: United States -- California
Source: MAI 55/04M(E), Masters Abstracts International
Subjects: Electrical engineering
Keywords: Binary adder, Quantum-dot cellular automata, Transistor size
Publication Number: 10108192
ISBN: 978-1-339-71555-1
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