Digital Signal Processing (DSP) processors are used in personal computers, smart phones, multimedia devices, etc. Traditional DSP processors with custom logic must meet the demand for increased processing speed. The main aim of the project is to design a 32-bit integer arithmetic processor and to implement it. This design has three major processing features. First, the speed must be optimized by using a hazard free control unit. Second, it must have a two stage pipeline. Third, a single cycle multiply accumulator is utilized. The main advantage of the two stage pipeline is that it can manipulate the instructions, and it can produce correct cycle timing even though there may be hazards. A reduced instruction set is used in this design. A filtering operation is included in order to differentiate the DSP processor from a traditional processor. The processor is designed using Harvard architecture in which both data memory and program memory are accessed simultaneously. This design increases the processing speed by 30%.
|Commitee:||Ary, James, Mangir, Tulin|
|School:||California State University, Long Beach|
|School Location:||United States -- California|
|Source:||MAI 55/04M(E), Masters Abstracts International|
|Keywords:||Arithmetic processors, Digital signal processing, Hazard free control units|
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