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Dissertation/Thesis Abstract

A SAR Fast-Locking Digital Phase-Locked Loops: Behavioral modeling and simulations using matlab/simulink
by Gentyala, Rakesh, M.S., California State University, Long Beach, 2016, 48; 10102588
Abstract (Summary)

A Successive-Approximation Register Fast-Locking Digital Phase-Locked Loop (SAR DPLL) is presented and behaviorally modeled using MATLAB/Simulink. The DPLL operation includes two stages: (1) a SAR coarse-tuning stage for frequency tracking, which employs a successive-approximation algorithm similar to the one employed in SAR A/D converters (ADCs) and (2) a fine-tuning stage for phase tracking, which is similar to conventional DPLLs. The coarse-tuning stage includes a phase frequency detector, a successive-approximation register, a D/A converter (DAC), and control logic. MATLAB/Simulink are used to design and perform simulations. The fast-locking DPLL saves about 50 percentage of the lock time as compared to its conventional DPLL counterpart.

Indexing (document details)
Advisor: Wagdy, Mahmoud
Commitee: Khoo, I-Hung, Wang, Fei
School: California State University, Long Beach
Department: Electrical Engineering
School Location: United States -- California
Source: MAI 55/04M(E), Masters Abstracts International
Subjects: Engineering, Electrical engineering
Keywords: Course tuning, Digital phase lock loop, Fast locking dpll, Frequency tracking, Sar algorithm, Successive approximation register
Publication Number: 10102588
ISBN: 978-1-339-66270-1
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