Network-On-Chip (NOC) technology requires high speed communications between the various parts on the chip such as the microprocessor, memory, digital signal processing modules (DSP), etc. As a result of their complexity, NOC architectures have high power requirements, which is a critical issue especially for portable battery-powered devices. In this project, various data encoding and decoding techniques are used in an attempt to reduce the power consumption on the NOC. Three data encoding schemes are presented and compared through simulations performed using the Verilog Hardware Description Language (VHDL). The results of the simulations show that two of the schemes reduce switching activities and consequently reduce power consumption to a considerable degree as compared to the baseline system.
|Commitee:||Ary, James, Tran, Boi|
|School:||California State University, Long Beach|
|School Location:||United States -- California|
|Source:||MAI 55/04M(E), Masters Abstracts International|
|Subjects:||Engineering, Electrical engineering|
|Keywords:||NOC architectures, Network on chip, Verilog hardware description language|
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