Dissertation/Thesis Abstract

Design, analysis, and synthesis of 16 bit arithmetic logic unit using reversible logic gate
by Midde, Bharath Reddy, M.S., California State University, Long Beach, 2016, 59; 10099864
Abstract (Summary)

In the modern world, an Arithmetic Logic Unit (ALU) is one of the most crucial component of an embedded system and is used in many devices like calculators, cell phones, computers, and so on. An ALU is a multi-functional circuit that conditionally performs one of several possible functions on two operands A and B depending on control inputs. It is nevertheless the main performer of any computing device. This project proposes the design of programmable reversible logic gate structures, targeted for the ALU implementation and their use in the realization of an efficient reversible ALU. This ALU consists of sixteen operations, the arithmetic operations include addition, subtraction, multiplication and the logical operations includes AND, OR, NOT and XOR. All the modules are being designed using the basic reversible gates.

Using reversible logic gates instead of traditional logic AND/OR gates, a reversible ALU is constructed whose function is the same as traditional ALU. Comparing with the number of input bits and the discarded bits of the traditional ALU, the reversible ALU significantly reduces the use and loss of information bits. The proposed reversible 16-bit ALU reuses the information bits and achieves the goal of lowering delay of logic circuits by 42% approximately. Programmable reversible logic gates are realized in Verilog HDL.

Indexing (document details)
Advisor: Yeh, Hen-Geul
Commitee: Ary, James, Chu, Chaw-Long
School: California State University, Long Beach
Department: Electrical Engineering
School Location: United States -- California
Source: MAI 55/04M(E), Masters Abstracts International
Source Type: DISSERTATION
Subjects: Electrical engineering
Keywords: Arithmetic logic unit, Reversible logic gates
Publication Number: 10099864
ISBN: 978-1-339-63820-1
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