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Dissertation/Thesis Abstract

A 100 MHz 6th Order Continuous Time Band-Pass Sigma Delta Modulator with Active Inductor Resonators
by Dobson, Kevin, Ph.D., The George Washington University, 2016, 115; 10085732
Abstract (Summary)

Band-Pass Sigma Delta Modulators allow for the digitization of a carrier signal directly without frequency down conversion to baseband. This results in a simpler and more economical RF receiver front end. The holy grail of signal processing is to develop a Band-Pass Analog to Digital Converter operating at a high enough frequency to digitize high frequency RF signals such as Wi-Fi or cell phone carriers without the need for complicated Filters, Mixers and Amplifiers in the receiver front end.

Continuous Time Band-Pass Sigma Delta Analog to Digital Converters are potentially one technology that can be used to realize this goal because of their ability to operate at higher frequencies than their switched capacitor counterparts. Current Continuous Time Band-Pass Sigma Delta Modulators utilize LC circuits as resonators. This leads to a design that occupies a large die area. In fact, in many designs the area of the spiral inductors occupies more than half the design area. Another drawback of using spiral inductors is the limited quality factor. In order for there to be a high dynamic range at the output of a sigma delta modulator it is necessary to have resonators with high quality factors. We investigate the effects of replacing spiral inductors with high quality factor active inductor resonators with negative impedance circuits.

CMOS is a fairly cheap technology when compared to other ASIC design technologies. It also offers lower power consumption but its operating frequencies are somewhat lower. We have chosen to use CMOS technology for our design because of its economy and low power consumption. We have been able to design and simulate a 6th order, continuous time Band-Pass Sigma Delta modulator in IBM 0.18u cmrf7sf CMOS technology. Cadence schematic simulations show a modulator with a high dynamic range and decreased area usage.

Pad to pad simulation of the extracted layout in Cadence yields an enhanced peak SNDR of 73 dB with a noise bandwidth of 36 kHz and a power consumption of 12 mW. This modulator occupies 2.05 mm2 of active die area.

Indexing (document details)
Advisor: Zaghloul, Mona, Ahmadi, Shahrokh
Commitee: Ahmadi, Shahrokh, Della Torre, Edward, Doroslovacki, Milos, Korman, Can, Zaghloul, Mona
School: The George Washington University
Department: Computer Engineering
School Location: United States -- District of Columbia
Source: DAI-B 77/08(E), Dissertation Abstracts International
Subjects: Computer Engineering, Electrical engineering
Keywords: Active inductor, CMOS, Sigma delta
Publication Number: 10085732
ISBN: 978-1-339-59098-1
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