Intermediate frequency (IF) sampling demands stringent tracking bandwidth and linearity performance of analog-to-digital converters (ADCs), dictating high supply voltages and bipolar devices to implement the front-end buffer/sampler. As quantizers are almost exclusively realized in scaled CMOS technology, the integration of the high-voltage bipolar front-end and the low-voltage CMOS quantizer becomes a challenging task as cost, form factor, and power consumption are important competitive metrics for vendors. In this work, we present a compact error correction model to linearize the sample-and-hold (S/H) circuits realized exclusively in low-cost CMOS technology for IF-sampling applications that can potentially achieve a spurious-free dynamic range (SFDR) of over 100 dB.

To achieve this goal, a derivative-based error model is developed to address the dynamic nonlinearity in CMOS S/H circuits, which is mainly attributed to the nonlinear on-resistance of the MOS transistors employed as a switch. Our analysis reveals that the nonlinearity of the switch resistance is primarily caused by the drain-source voltage modulation effect. Based on this observation, a compact derivative-based error model is proposed for dynamic nonlinearity calibration, which obviates complex Volterra models commonly encountered in literature to address similar problems. An analog high-pass filter (HPF) derivative-estimation technique is further proposed to obtain direct derivative information (DDI) of the analog input as opposed to using digital interpolation filters that suffer from bandwidth limitations. The S/H error model is also further simplified due to the availability of DDI with reduced digital computing load. A 65-nm CMOS S/H circuit with an accompanying analog derivative filter is designed at transistor level and simulated in Spectre. The results are post-processed using the proposed calibration model in MATLAB. The SFDR of the S/H is improved from 70 dB to over 100 dB for input frequencies up to 500 MHz.