The concern about energy consumption in current technology node is becoming more serious. As we are already in deep sub-micron era, the relentless process scaling makes existing energy reduction techniques less efficient. It is predicted that we might soon face the situation where most of the silicon area is forced to be dark and can not be powered on simultaneously.
As alternative solutions, a number of emerging memory technologies are being actively studied. They allow us to design more energy efficient architectures and potentially solve the dark silicon problem from the ground. However, they also incur certain weaknesses such as high write energy and limited endurance. Previous studies showed that an effective way to mitigate these negative impacts is by optimizing the memory architecture.
Therefore, this thesis will focus on architecture designs for deploying emerging memories at various levels in the memory hierarchy. (Abstract shortened by UMI.)
|School:||National University of Singapore (Singapore)|
|School Location:||Republic of Singapore|
|Source:||DAI-B 77/06(E), Dissertation Abstracts International|
Copyright in each Dissertation and Thesis is retained by the author. All Rights Reserved
The supplemental file or files you are about to download were provided to ProQuest by the author as part of a
dissertation or thesis. The supplemental files are provided "AS IS" without warranty. ProQuest is not responsible for the
content, format or impact on the supplemental file(s) on our system. in some cases, the file type may be unknown or
may be a .exe file. We recommend caution as you open such files.
Copyright of the original materials contained in the supplemental file is retained by the author and your access to the
supplemental files is subject to the ProQuest Terms and Conditions of use.
Depending on the size of the file(s) you are downloading, the system may take some time to download them. Please be