Complementary-metal-oxide-semiconductor (CMOS) transistors have been commonly employed in the electronics for the past decades due to their excellent scalability, low cost, and high performance. Higher packing density per unit chip area and enhanced circuit performance can be achieved via the scaling of CMOS transistors. However, with the scaling of CMOS devices into the nanometer regime, the issues associated with the adverse short channel effects (SCEs) arise, leading to high leakage current which increases the static power of a transistor. Furthermore, exponential growth of the number of transistors per integrated circuit (IC) chip causes drastic increase of power density. All these contribute to high power consumption in an IC chip, which has become a serious problem as the technology advances.
In order to reduce the power consumption, power supply voltage ( VDD) needs to be lowered. Nevertheless, reduction of VDD should not compromise the ON-current (I ON) so that the switching speed of transistors can be sustained. In this context, metaloxide- semiconductor field-effect transistors (MOSFETs) based on alternative channel materials with high product of carrier velocity and density of states (DOS) and tunneling field-effect transistor (TFET) with steeper subthreshold slope (S) are promising candidates to enable the reduction of VDD. In this thesis, MOSFETs with alternative potential channel materials and TFET are explored. (Abstract shortened by UMI.)
|School:||National University of Singapore (Singapore)|
|Department:||Electrical and Computer Engineering|
|School Location:||Republic of Singapore|
|Source:||DAI-B 77/06(E), Dissertation Abstracts International|
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