The aggressive downscaling of complementary metal-oxide-semiconductor (CMOS) is facing great challenges due to fundamental limitations and practical considerations. To continue scaling beyond 14 nm technology node, various architectural and material changes in the traditional MOSFET would be required for efficient operation of the transistor as a switch. Among several emerging nanoscale devices, III-V MOSFETs are one of the most attractive devices due to their extremely high electron mobility. However, new processes associated with III-V substrates must be simplified, and costs of integration on Si substrate should be reduced. This thesis aims to address the various challenges in realizing short channel III-V MOSFETs on silicon for sub-7 nm logic applications. (Abstract shortened by UMI.)
|School:||National University of Singapore (Singapore)|
|Department:||Electrical And Computer Engineering|
|School Location:||Republic of Singapore|
|Source:||DAI-B 77/06(E), Dissertation Abstracts International|
|Subjects:||Computer Engineering, Electrical engineering|
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