Digital multipliers are among the most critical arithmetic functional units in many digital systems. The overall performance of these digital systems is determined by the throughput of the multiplier. Aging in the transistor occurs due to negative bias or positive bias temperature instability. Both effects decrease transistor speed, and, in the long term, the system may fail due to timing violations. The current project presents the design of an aging-aware variable-latency multiplier based on an adaptive hold logic (AHL) circuit. This multiplier design provides higher throughput with the help of a variable-latency technique, and it can adjust the AHL circuit to reduce performance degradation that is due to the aging effect. Moreover, the proposed architecture can also be applied to a column bypassing multiplier or row bypassing multiplier that can further improve the performance. The simulation results show that our proposed architecture with 4 x 4 and 8 x 8 column bypassing multiplier and row bypassing multiplier has advantages such as reduced circuit delay and low power consumption.
|Commitee:||Ary, James, Moussavi, Maryam|
|School:||California State University, Long Beach|
|School Location:||United States -- California|
|Source:||MAI 55/03M(E), Masters Abstracts International|
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