Emerging 3D die-stacked DRAMs is a promising solution to satisfy the everincreasing demands of computer systems on memory throughput, power efficiency, capacity, and cost. This dissertation seeks to model and design 3D DRAM memory systems with high performance and high power-efficiency from micro-architecture level to system level.
This dissertation introduces CACTI-3DD, the first architecture-level integrated power, area, and timing modeling framework for 3D die-stacked DRAM main memory. CACTI-3DD incorporates TSV models, improves models for 2D off-chip DRAM main memory over current versions of CACTI, and includes 3D integration models that enable the analysis of a full spectrum of 3D DRAM designs at various stacking granularities. CACTI-3DD enables an in-depth study of architecture level tradeoffs of power, area, and timing for 3D die-stacked DRAM designs. (Abstract shortened by UMI.)
|Advisor:||Brockman, Jay B.|
|School:||University of Notre Dame|
|School Location:||United States -- Indiana|
|Source:||DAI-B 77/04(E), Dissertation Abstracts International|
|Subjects:||Computer Engineering, Electrical engineering|
|Keywords:||3d stacking, Cacti, Dram stack, Dynamic random access memory, Hybrid memory cubes, Row buffer cache|
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