Dissertation/Thesis Abstract

Low-power pulse-triggered flip-flop design based on a signal feed-through scheme
by Renukaiah, Vishwas, M.S., California State University, Long Beach, 2015, 38; 1601314
Abstract (Summary)

In this project, a novel pulse-triggered flip-flop design is proposed, which employs a modified True Single Phase Clock (TSPC) latch structure with a mixed style design consisting of pass transistor and pseudo nMOS logic. The proposed flip-flop design adopts a signal feed-through technique to improve the delay recovery, and achieves better performance in terms of speed and power consumption. The proposed flip-flop design has a weak pull-up pMOS transistor with gate connected to the ground in the first stage of TSPC latch. This structure is a pseudo nMOS logic style design. Post layout simulation results using CMOS 120nm technology affirms that in the proposed design delay is reduced when compared to existing system.

Indexing (document details)
Advisor: Chassiakos, Anastasios
Commitee: Ary, James, Khoo, I-Hung
School: California State University, Long Beach
Department: Electrical Engineering
School Location: United States -- California
Source: MAI 55/02M(E), Masters Abstracts International
Source Type: DISSERTATION
Subjects: Electrical engineering
Keywords: Conditional discharge, Implicit type flip-flop, Low power, Pulse triggered flip-flop, Signal feed-through scheme
Publication Number: 1601314
ISBN: 9781339123851
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