Today’s digital signal processing systems are dominated by the complexity of bit-parallel Multiple Constant Multiplications (MCMs). Various architectures and algorithms are being introduced in order to address this complexity problem. But, little or no attention is being given to alternative methods such as Shift add/subtract. In this report, I address this problem and find a solution to the complexity issue using Verilog HDL and FPGA Spartan 3.
|Commitee:||Ary, James, Chassiakos, Anastasios|
|School:||California State University, Long Beach|
|School Location:||United States -- California|
|Source:||MAI 55/02M(E), Masters Abstracts International|
|Keywords:||Finite impulse response filters|
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