Complex arithmetic operations are a critical part of Digital Signal Processing (DSP) applications. The main objective of this project is to improve the performance of DSP computations by optimizing the design of the Fused Add-Multiply (FAM) operator. We used a structured and efficient recoding technique and studied three different schemes by incorporating them into FAM designs. In the current project we proposed a technique to implement the direct recoding of the sum of two numbers in its Modified Booth (MB) form. Simulation results show that considerable reductions in terms of critical delay, hardware complexity and power consumption of the FAM unit have been achieved with the proposed technique as compared to existing recoding schemes used in the FAM designs.
|Commitee:||Ary, James, Chu, Chaw-Long|
|School:||California State University, Long Beach|
|School Location:||United States -- California|
|Source:||MAI 55/02M(E), Masters Abstracts International|
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