This thesis consists of a 28 nm submicron circuit design for high speed transceiver circuits used in high-speed wireline communications that operate in the 60 Gb/s range. This thesis is based on research done on high speed equalizer standards for the USB 3.1 SuperSpeed Differential Channel Loss Receiver Equalizer or Peripheral Component Interconnect (PCI) Express ® Base Specification Revision 3.0. As of 2015, USB 3.1 and PCI Express® 3.0 are technologies with possibilities to be implemented in emerging technology targeted to consumer applications that demand improvements in signal integrity for high speed serial data communication of baud rates above 20 Gb/s. This thesis proposes a circuit design for an adaptive equalizer capable of adjusting its voltage gain, bandwidth, and boost for high speed data communications. The proposed design is implemented with a novel variable gain amplifier (VGA), a digitally controlled continuous time linear equalizer (CTLE), and a digitally controlled decision feedback equalizer (DFE), which is believed to provide circuit power and signal integrity improvements in the differential receiver and equalization subsystem that operate at 60 Gb/s .
|Advisor:||Ardalan, Shahab, Hamedi-Hagh, Sotoudeh|
|Commitee:||Le, Thuy T., Morelos-Zaragoza, Robert|
|School:||San Jose State University|
|School Location:||United States -- California|
|Source:||MAI 54/06M(E), Masters Abstracts International|
|Keywords:||28 nm, CMOS, Equalizer|
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