A major milestone in the evolution of video coding standards is the well-known H.264/MPEG-4 Advanced Video Coding (AVC). In January 2013 that was followed by H.265/MPEG-5 High-Efficiency Video Coding (HEVC). Both of these standards achieve substantial improvement in bit-rate efficiency compared to their predecessor and are the standard of choice in many application standards such as HD, DVD, HD-DTV.
With the proliferation of handheld devices, emphasis on reducing power consumption and increasing battery life is growing, thus making the improvement of power efficiency the main goal of any decoder implementation. However, most of the current power solutions focus solely on reducing memory accesses, the largest power drain. Other aspects that are not getting as much attention include memory access efficiency, memory power down, and pipeline efficiency. Power for these aspects can be reduced with new architectures for Memory Access Arbitration and Reference Data Scheduling. As shown in this work, using these techniques results in 87.67% off chip memory power reduction and reduces the number of memory accesses by 86.9% when the memory is power up.
|School:||North Carolina State University|
|School Location:||United States -- North Carolina|
|Source:||DAI-B 76/11(E), Dissertation Abstracts International|
|Subjects:||Computer Engineering, Electrical engineering, Computer science|
|Keywords:||H.264, H.265, Low power techniques, Memory arbitration, Motion compensation, Off chip memory, Video codec|
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