The rise of cloud computing and advanced network services like online video/audio has continuously driven the demand for higher wireline communication bandwidth. It brings on multiple challenges of serial link transceiver design with higher speed operation, more sophisticated equalization, better energy eciency, lower cost, and robust against process, voltage, and temperature variations (PVT) variations. This dissertation focuses on two essential blocks in a serial link transceiver which are phase-locked loop (PLL) and equalizer. Several new circuit design techniques are proposed in order to achieve a robust and power-ecient data link. Specically: (I) A wideband and low-jitter PLL is designed, in which a novel LC-VCO temperature drift compensation scheme is proposed. Unlike the conventional solution, the proposed scheme does not aect the LC-VCO tuning range and phase noise. It allows the PLL to cover an octave frequency tuning range of 6∼12GHz by using only two LC-VCO cores and remain locked within the temperature range of -40°C∼85°C no matter what temperature the PLL is initially locked at. The prototype PLL has been fabricated in TSMC 130nm technology and the proposed concept has been veried. Measurements show that the PLL covers a 5.6∼13.4GHz tuning range while remaining locked -40°C∼85°C. At 25°C, the PLL achieves an RMS random jitter (RJRMS) of 0.37ps at 11.44GHz. The integrated jitter is less than 0.7ps over the entire tuning range and varies less than 50fs over temperature. The PLL consumes 50.88mW power from a 1.2V supply at 12GHz and 25°C. This PLL provides a robust timing solution for multi-data rate serial link applications. (II) A power-ecient equalizing receiver is designed, in which a novel non-50% duty-cycle clocking scheme is proposed. It allows the StrongArm latch-based half-rate 1-tap speculative decision feedback equalizer (DFE) to operate 20% faster than the conventional solution. The prototype receiver has been fabricated in TI 65nm digital technology with only normal Vt transistors and the proposed concept has been veried. Measurements show that the receiver can operate up to 21Gb/s over a 25dB loss channel with PRBS−31 data pattern. The power consumption is 20.08mW including that from the non-50% duty-cycle clock generation circuitry and the clock buers. This receiver equalizer provides a power-ecient and power-scalable equalization solution for multi-data rate serial link applications on moderate-loss channels. (III) A radiation-hardened ring PLL is designed, in which three radiation-hardened-by-design (RHBD) techniques are proposed to eliminate or mitigate SEE. Firstly, all the sequential logic blocks are implemented by using DICE cell. The DICE cell timing parameters are optimized to make it immune to SET at its inputs. Secondly, a cross-coupled ring VCO is proposed to mitigate SET inside the VCO by a factor of two. Lastly, a charge compensation scheme along with its control block are proposed to mitigate SET at the output of charge pump, the most SET vulnerable node in a PLL. It reduces the SET-induced VCO control voltage disturbance by a factor of 2∼4. A protoypte PLL is implemented in GF 130nm digital technology. Post-layout simulations have been conducted in order to verify the validity of the proposed techniques. The PLL covers a 12.5∼500MHz tuning range with an RJRMS of 4.9ps and consumes 21.5mW power from a 1.5V supply.
|Commitee:||Camp, Joseph, Chen, Jinghong, Peikari, Behrouz, Rajan, Dinesh, Thornton, Mitchell|
|School:||Southern Methodist University|
|School Location:||United States -- Texas|
|Source:||DAI-B 76/09(E), Dissertation Abstracts International|
|Keywords:||DFE, Pll, RHBD, See, Serdes, Wireline|
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