As the power densities increase in integrated circuits (IC) nowadays, especially in 3 dimensional IC (3D-IC), power-induced thermal effects become more and more severe. Therefore, thermal analysis is becoming increasingly important for IC design. The aim of this thesis is to develop power and thermal modeling techniques and the verification method to address the power and thermal challenges in IC designs. The work of this thesis is done by the support of the Vertical Integrated Pattern Recognition Associated Memory (VIPRAM) project from Fermilab. Using the proposed techniques, a power and a thermal model for proto-VIPRAM chip have been developed respectively. Treating one CAM cell as a single power source is found to result in best trade-off between accuracy and speed. A practical verification method for the two modeling approach, which is suitable with the capability of current circuit simulator and thermal sensor system, has been proposed as well. Considering the special power property of the proto-VIPRAM compared to conventional CPU or DRAM chip, the optimization for the input pattern, which can cause the maximum temperature variation across the chip, has also been researched and found. The simulation results provide a good reference to the design of VIPRAM in the next stage. The proposed modeling and analysis methods for power and thermal issues can be also used in other chips for High Energy Physics (HEP) application.
|Commitee:||Dworak, Jennifer, Gosney, William M., Raad, Peter|
|School:||Southern Methodist University|
|School Location:||United States -- Texas|
|Source:||MAI 54/01M(E), Masters Abstracts International|
|Keywords:||Associative memory, Power, Temperature, Thermal, Trigger|
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