In digital integrated circuit design the need for synchronization of data across clock domains is still an issue that has proven to be difficult to many engineers and designers today. The risk of metastability is becoming much larger due to increasingly shrinking feature sizes. Designs that enter the deep sub-micron realm are more prone to variations in process.
This thesis will analyze and process, voltage, and temperature (PVT) variation and its effects upon CMOS technologies. Formal sensitivity analysis will be used throughout this thesis as a mathematical method of describing variability of PVT. These ideas will form a set of suggestions to help make designs tolerant of such variations. A method will also be introduced to predict values of the key metastability parameter τ in the presence of variation with the knowledge of a single value. The methods presented are tested on two vastly circuit topologies and have extremely accurate results.
The first synchronizer circuit discussed is just a typical data register. The relationship between τ and GBW is derived as a method for sizing devices. Using the sensitivity equations developed. The correlation coefficients for all of the designs and PVT variations was found to be above 0.98 in all cases. The maximum error between simulated and predicted data was 37%, and found in the threshold prediction section. This was due to moderate inversion.
The second synchronizer circuit discussed is a topology designed specifically to be a synchronizer. This topology is sized in the same manner as the first synchronizer. The benefits of such a design are proven before sensitivity analysis is applied. The vastly different topology chosen is intended to show the robustness of the sensitivity analysis method for any topology. The variability of the metastable voltage is compared between designs and for a sweeping supply, the slope for the second synchronizer's metastable voltage is found to be 0.35 V/V on average. The correlation coefficient of the predicted values using the equations and the simulated values was found to be above 0.98 in all applied analyses.The maximum error in any of the analyses was only 10% from the predicted value.
The proposed sensitivity analysis is shown to work well in different situations. The analytical method proposed works well for PVT variation tolerant design, as long as the sensitivity equations are properly derived for the specific topology
|Advisor:||Engel, George L.|
|Commitee:||Engel, George L., Noble, Bradley, Smith, Scott|
|School:||Southern Illinois University at Edwardsville|
|Department:||Electrical and Computer Engineering|
|School Location:||United States -- Illinois|
|Source:||MAI 53/06M(E), Masters Abstracts International|
|Keywords:||Metastability, Sensitivity, Synchronizer, Variability|
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