Ever decreasing cost of electronics due to unique scaling potential of today's VLSI processes such as CMOS technology along with innovations in RF devices, circuits and architectures make wireless communication an un-detachable part of everyday's life. This rapid transition of communication systems toward wireless technologies over last couple of decades resulted in operation of numerous standards within a small frequency window. More traffic in adjacent frequency ranges imposes more constraints on the linearity of RF front-end stages, and increases the need for more effective linearization techniques. Long-established ways to improve linearity in DSM CMOS technology are focused on system level methods which require complex circuit design techniques due to challenges such as nonlinear output conductance, and mobility degradation especially when low supply voltage is a key factor. These constrains have turned more focus toward improvement of linearity at the device level in order to simplify the existing linearization techniques. This dissertation discusses the possibility of employing nanostructures particularly nanowires in order to achieve and improve RF linearity at the device level by making a connection between the electronic transport properties of nanowires and their circuit level RF characteristics (RF linearity). Focus of this work is mainly on transconductance (gm) linearity because of the following reasons: 1) due to good electrostatics, nanowire transistors show fine current saturation at very small supply voltages. Good current saturation minimizes the output conductance nonlinearities. 2) non-linearity due to the gate to source capacitances (Cgs) can also be ignored in today's operating frequencies due to small gate capacitance values. If three criteria: i) operation in the quantum capacitance limit (QCL), ii) one-dimensional (1-D) transport, and iii) operation in the ballistic transport regime are met at the same time, a MOSFET will exhibit an ideal linear Id-Vgs characteristics with a constant gm of which is independent of the choice of channel material when operated under high enough drain voltages. Unique scaling potential of nanowires in terms of body thickness, channel length, and oxide thickness makes nanowire transistors an excellent device structure of choice to operate in 1-D ballistic transport regime in the QCL. A set of guidelines is provided for material parameters and device dimensions for nanowire FETs, which meet the three criteria of i) 1-D transport ii) operation in the QCL iii) ballistic transport, and challenges and limitations of fulfilling any of the above transport conditions from materials point of view are discussed. This work also elaborates how a non-ideal device, one that approaches but does not perfectly fulfill criteria i) through iii), can be analyzed in terms of its linearity performance. In particular the potential of silicon based devices will be discussed in this context, through mixture of experiment and simulation. 1-D transport is successfully achieved in the lab. QCL is simulated through back calculation of the band movement of the transistors in on-state. Quasi-ballistic transport conditions can be achieved by cooling down the samples to 77K. Since, ballistic transport is challenging to achieve for practical channel lengths in today's leading semiconductor device technologies the effect of carrier back-scattering on RF linearity is explored through third order intercept point (IIP3) analysis. These findings show that for the devices which operate in the QCL, while 1-D sub-bands are involved in carrier transport, current linearity is directly related to the nature of the dominant scattering mechanism in the channel, and can be improved by proper choice of channel material in order to enforce a specific scattering mechanism to prevail in the channel. Usually, in semiconductors, the dominant scattering mechanism in the channel is the superposition of different mechanisms. Suitable choice of channel material and bias conditions can magnify the effect of a particular scattering mechanism to achieve higher linearity levels. The closing section of this thesis focuses on InAS due to its potential for high linearity since it has small effective mass and large mean-free-path.
|Advisor:||Appenzeller, Joerg, Janes, David|
|Commitee:||Jung, Byunghoo, Yang, Chen|
|Department:||Electrical and Computer Engineering|
|School Location:||United States -- Indiana|
|Source:||DAI-B 76/02(E), Dissertation Abstracts International|
|Subjects:||Electrical engineering, Nanotechnology|
|Keywords:||1-d transport, Linearity, Mosfet, Nanowire, Schottky barrier, Transconductance|
Copyright in each Dissertation and Thesis is retained by the author. All Rights Reserved
The supplemental file or files you are about to download were provided to ProQuest by the author as part of a
dissertation or thesis. The supplemental files are provided "AS IS" without warranty. ProQuest is not responsible for the
content, format or impact on the supplemental file(s) on our system. in some cases, the file type may be unknown or
may be a .exe file. We recommend caution as you open such files.
Copyright of the original materials contained in the supplemental file is retained by the author and your access to the
supplemental files is subject to the ProQuest Terms and Conditions of use.
Depending on the size of the file(s) you are downloading, the system may take some time to download them. Please be