Designers utilizing tools and workflows in place at The George Washington University may encountered several roadblocks, including the inability to create Design for Test (DFT) integrated circuits, inflexible pad-frames and a difficult to program logic analyzer, which records data into a proprietary output. This project demonstrated a low cost and quick time-to-market method for building and characterizing scan cells, allowing designers to easily build Design For Test (DFT) integrated circuits. A successful prototype scan cell has been manufactured and tested, utilizing a modular padframe obtained from the University of Utah. An approach to creating low-cost test harnesses has been demonstrated by converting Verilog test benches to the Arduino Wiring platform,. An algorithm and implementation for converting data captured from Agilent logic analyzers to the IEEE VCD format is presented. This work has important implications for future development of design flows, additional low-cost test harnesses and test-focused educational curriculum.
|Commitee:||Ahmadi, Shahrokh, Korman, Can E.|
|School:||The George Washington University|
|School Location:||United States -- District of Columbia|
|Source:||MAI 53/03M(E), Masters Abstracts International|
|Subjects:||Computer Engineering, Electrical engineering, Computer science|
|Keywords:||Dft, Logic analyzer, Scan chain, Standard cell, Test bench, Vlsi|
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