Dissertation/Thesis Abstract

Dynamic Load-Based Power and Clock Gating Techniques for High-Speed Digital Circuits
by Farah, Salim, Ph.D., University of Louisiana at Lafayette, 2014, 128; 3622218
Abstract (Summary)

High-performance CPUs commonly deployed in data-centers accumulate a significant amount of energy and run in the millions of kilowatts per year. This family of CPUs can highly benefit from low power techniques that do not negatively impact performance. This work addresses the issue by offering two power optimization schemes that automatically trigger based on the activity level. First is CEMS-PG, a power-gating technique with low ground bounce noise, allowing for fast wakeups and response time from deep sleep states. Our simulations show up to 44% improvement in wakeup time and 78% in peak noise, offering minimal compromise between the two. Second is Reactive Domino, a clock gating scheme for Domino circuits with dynamic frequency scaling. Through efficient switching activity detection, activity-domain partitioning, and a specific multi-phase clocking configuration based on skew-tolerant Domino, clusters of gates can be prevented from unnecessary switching while preserving logic integrity. For activity in the first half of operands, savings from 31% to 44% were observed, while worst case power overhead ranged from 2.5% to 12.5% depending on the methodology used. Finally, this work presents OAPM, a low-level power management technique that relies on activity level in the operand. It ties together CEMS-PG and Reactive Domino, employing a fast-acting algorithm for dynamically switching between these two power states and a 3 rd turbo mode for maximum performance.

Indexing (document details)
Advisor: Bayoumi, Magdy
Commitee: Kumar, Ashok, Madani, Mohammad, Perkins, Dmitri
School: University of Louisiana at Lafayette
Department: Computer Engineering
School Location: United States -- Louisiana
Source: DAI-B 75/10(E), Dissertation Abstracts International
Source Type: DISSERTATION
Subjects: Computer Engineering
Keywords: Clock gating, Digital circuits, Domino logic, Low power, Power gating
Publication Number: 3622218
ISBN: 978-1-303-93847-4
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