Dissertation/Thesis Abstract

Energy Scavenging in Three Dimensional Integrated Circuits with Through Silicon Vias
by Minvielle, Robert, Ph.D., University of Louisiana at Lafayette, 2013, 132; 3615292
Abstract (Summary)

Modern high performance Integrated Circuits (ICs) are pushing the limits of Two Dimensional (2D) planer technologies in terms of power and frequency scaling. Manufacturers and researchers are looking at the Three Dimensional (3D) IC as a method to overcome power delivery and wire scaling problems of the current 2D technology. Modern designs must also be power efficient. This dissertation proposes a new method of energy scavenging in high performance 3D ICs using one of the building blocks of building a 3D IC as an energy scavenging device. The method put forth here differs from traditional energy scavenging in that the power that would normally be shunted to ground to prevent noise and crosstalk will be used to charge a decoupling capacitor within the 3D IC. This research sets out to answer the feasibility of such a system, and to find an optimalsolution if there is one. This research was performed by studying the current Through Silicon Via (TSV) technology and noting that most signal TSV are surrounded by guard rings madeup of TSVs used to shunt the coupling between the TSV and other parts of the circuit to ground. Simulations were preformed to study the feasibility of scavenging the power that was being shunted to ground and storing it, particularly in on-board decoupling capacitors. After initial TSV to TSV coupling results were confirmed, the decoupling capacitor and associated circuitry were added and studied. It was shown that the decoupling capacitor can be reliably charged to more than one-half of the incoming signal voltage in less than fifty pulses, even with large decoupling capacitors and over a wide range of signal frequencies. With one volt square wave signals a decoupling capacitor of size 200ƒF can be charged to 0.537 volts using a 45nm by 400nm MOSFET in 500ns. Similarly a 50ƒF decoupling capacitor can be charged to 0.5453 volts using a 45nm by 4800nm MOSFET in 25 ns. It has been shown in this dissertation that is is possible to scavenge power from a system which normally shunts this power to ground, and it can be stored for later use.

Indexing (document details)
Advisor: Bayoumi, Magdy
Commitee: Madani, Mohammad, Tzeng, Nian-Feng, Zhao, Danella
School: University of Louisiana at Lafayette
Department: Computer Engineering
School Location: United States -- Louisiana
Source: DAI-B 75/07(E), Dissertation Abstracts International
Subjects: Computer Engineering
Keywords: 2D, 3D, Energy scavenging, Integrated circuits, Silicon Vias, Three dimensional Integrated Circuits
Publication Number: 3615292
ISBN: 978-1-303-81189-0
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