Dissertation/Thesis Abstract

Toward a Hardware Accelerated Future
by Lyons, Michael John, Ph.D., Harvard University, 2013, 162; 3600206
Abstract (Summary)

Hardware accelerators provide a rare opportunity to achieve orders-of-magnitude performance and power improvements with customized circuit designs.

Many forms of hardware acceleration exist—attributes and trade-offs of each approach is discussed. Single-algorithm accelerators, which maximize efficiency gains through maximum specialization, are one such approach. By combining many of these into a many-accelerator system, high specialization is possible with fewer specialization limits.

The development of one such single-algorithm hardware accelerator for managing compressed Bloom filters in wireless sensor networks is presented. Results from the development of the accelerator highlight scalability deficiencies in the way accelerators are currently integrated into processors, and that the majority of accelerator area is consumed by generic SRAM memory rather than algorithm-specific logic.

These results motivate development of the accelerator store, a system architecture designed for the needs of many-accelerator systems. In particular, the accelerator store improves inter-accelerator communication and includes support for sharing accelerator SRAM memories. Using a security application as an example, the accelerator store architecture is able to reduce total processor area by 30% with less than 1% performance overhead.

Using the accelerator store as a base, the ShrinkFit framework allows accelerators to grow and shrink, to achieve accelerated performance within small FPGA budgets and efficiently expand for more performance when larger FPGA budgets are available. The ability to resize accelerators is particularly useful for hybrid systems combining GP-CPUs and FPGA resources, in which applications may deploy accelerators to a shared FPGA fabric. ShrinkFit performance overheads for small and large FPGA resources are found to be low using a robotic bee brain workload and FPGA prototype.

Finally, future directions are briefly discussed along with details about the production of the robotic bee helicopter brain prototype.

Indexing (document details)
Advisor: Brooks, David M., Wei, Gu-Yeon
Commitee: Brooks, David, Wei, Gu-Yeon, Wood, Robert J.
School: Harvard University
Department: Engineering and Applied Sciences
School Location: United States -- Massachusetts
Source: DAI-B 75/02(E), Dissertation Abstracts International
Subjects: Computer Engineering, Computer science
Keywords: Compressed Bloom filters, Hardware acceleration, Wireless sensor networks
Publication Number: 3600206
ISBN: 978-1-303-50260-6
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