Solid phase crystallization (SPC) is a processing technique used for conversion of amorphous silicon (a-Si) to polycrystalline silicon (poly-Si). SPC can potentially be used as an alternative to excimer laser annealing to fabricate the semiconductor layer for thin-film transistors (TFTs) in active-matrix liquid crystal display (AMLCD). It is a technique suitable for large-area applications since it involves easily scalable thermal processes in the form of rapid thermal annealing (RTA) and furnace annealing (FA). The SPC parameter space involves the time and temperature of the FA, and the time, temperature, and number of pulses in the RTA process.
In developing new process flows for thin-film transistors (TFTs) using SPC, thermal and electrical device simulation are invaluable tools. Comsol ® was utilized to explore this SPC experimental parameter space, and provided important insight on temperature conditions not directly measureable on glass substrates (see Fig. 1). Silvaco's Atlas® was utilized to evaluate the TFT response variables of sub-threshold slope (SS), threshold voltage (VT), and maximum current (I max). Further, a procedure for fitting TFT device characteristics using Atlas was developed. From this simulation fit (see Fig. 2), theoretical trap state distributions for the semiconducting film can be extracted, as well as the trap state distributions at the oxide-semiconductor interfaces.
|Commitee:||Pearson, Robert, Rommel, Sean|
|School:||Rochester Institute of Technology|
|School Location:||United States -- New York|
|Source:||MAI 52/02M(E), Masters Abstracts International|
|Keywords:||Device, Physics, Polycrystalline, Semiconductor, Silicon, Thin film transistor|
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