Semiconductor manufacturing companies aim to achieve shortest test times for products while maintaining the product quality. Achieving shortest test times for devices requires multiple updates to the test flow and test content. Test cost varies in direct proportion to production test time required to test chips and detect fails. This thesis presents a method to achieve shortest test times by determining when the updates are needed and what are the changes to the test flow and test content.
This thesis introduces a new Adaptive Test Scheme (ATS). ATS estimates individual test fail rates dynamically, per die, and makes real-time modifications to test order and test contents. ATS computes data-driven test fail rate estimates and uses the estimates to identify the required changes and trigger updates to test flow and test content. ATS uses Bayesian statistics to model the per test fail rates and update the test orders. ATS achieves test time reductions by employing per wafer elimination. ATS also incorporates a simple quality monitor, by resetting the test content at the start of next wafer.
This thesis evaluates the performance of ATS with synthetic data generated by a Monte Carlo method and with production wafer sort data for two manufactured products. The product data results show ATS reduced by 20% the total test-time for one product and by 40% for a second product, with changes in product quality level below industry targets.
|Advisor:||Daasch, W. Robert|
|Commitee:||Faust, Mark, Shirley, Glenn C.|
|School:||Portland State University|
|Department:||Electrical and Computer Engineering|
|School Location:||United States -- Oregon|
|Source:||MAI 51/02M(E), Masters Abstracts International|
|Keywords:||Adaptive ic test, Ic test, Semiconductor test cost, Test reordering, Test time reduction|
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