Security is paramount in modern Information Technology (IT) systems, and cryptography is a crucial component of data integrity and confidentiality. However, executing cryptography applications on general-purpose processors raises two concerns: performance and security. First, cryptography applications have very high performance overhead due to their high transmission rate and large number of computational operations. Also, if purely implemented by software, they can be tampered by some malicious but smarter malware. The purpose of this research is to address these two issues by using computer architecture methodology to enhance security / cryptography mechanisms in modern industrial and academic technologies.
This dissertation completed a workload characterization on a selected set of cryptographic benchmarks. Their characteristics of program structures and arithmetic / logic operations are representative of modern cryptography design. Upon characterizing these structures and operations, their performance-intensive parts were determined. Then the performance of these hotspots of cryptography algorithms was evaluated in the computational and memory perspective on different architectures. The identified hotspot (performance-intensive) part of each benchmark is implemented into hardware. The results demonstrated that hardware assisted solution for cryptography application can achieve superior performance, low hardware cost, and low power consumption.
The dissertation also demonstrates that memory access operations are the real performance bottleneck that is overlooked by previous research. It proposes the concept Load-Store Block (LSB)—a pair of Load and Store instructions with the same effective address, and with some instructions inside the block. Thus, Processor-in-Memory (PIM) was chosen to be a suitable architecture. The low latency, high memory bandwidth, and high data-parallelism features of PIM features are suitable for the LSB-Memory Bound application in asymmetric and some modes of symmetric encryption algorithms where data can be processed in parallel. Also, the hardware's feature that no pins or buses are exposed between the processor and memory will make it difficult for hardware attack, thus improving the architecture's security. In addition, PIM can be reconfigured to implement the new cryptography standard design or deal with some potential attack immediately. Our results show that it has a superior performance with low hardware cost and power consumption compared to other software implementations.
|School:||University of California, Irvine|
|Department:||Electrical and Computer Engineering - Ph.D.|
|School Location:||United States -- California|
|Source:||DAI-B 73/12(E), Dissertation Abstracts International|
|Keywords:||Cryptography, Flexible architectures|
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